The present invention relates to a semiconductor memory card, a method of controlling the semiconductor memory card and an interface apparatus for semiconductor memory card.
Semiconductor memory cards with a minimized number of terminals and interface standards for the semiconductor memory cards have been proposed for size reduction of semiconductor memory cards and host apparatuses of the semiconductor memory cards. A prior art semiconductor memory card will be described with reference to FIG. 8 and FIG. 9. FIG. 8 is a block diagram of the already proposed prior art semiconductor memory card (including an internal block diagram of an interface circuit of the semiconductor memory card). In FIG. 8, the semiconductor memory card 801 comprises: a data storing part 802 including a flash memory, a DRAM, an SRAM and the like for storing data; a control circuit 803 writing and reading data into and from the data storing part 802; an interface circuit 804 performing data input and output with the host apparatus; and a connection terminal 805.
As an example of the semiconductor memory card 801, one prior art semiconductor memory card has been proposed that supports two kinds of interface standards as shown in FIG. 9 in order that the semiconductor memory card is adaptable to diversification of interface specifications of host apparatuses. FIG. 9 shows the attributes and the functions allotted to nine terminals of the prior art semiconductor memory card supporting the two kinds of interface standards when the semiconductor memory card operates according to the two interface standards (a first operation mode and a second operation mode). A first terminal structure (first operation mode) and a second terminal structure (second operation mode) are as shown in FIG. 9. Of the structures based on the specifications of the two kinds of operation modes shown in FIG. 9, the structure based on the interface specification of the second operation mode is shown in FIG. 8.
In the structure of FIG. 8, the attribute of a terminal 1 of the connection terminal 805 is “input”, and the function allotted thereto is “chip select input”. The terminal 1 inputs a command signal CS to the control circuit 806 through a buffer 810. The attribute of a terminal 2 is “input”, and the function allotted thereto is “data input”. The terminal 2 inputs input data DI to the control circuit 806 through a data input buffer 807. The attribute of a terminal 5 is “input”, and the function allotted thereto is “clock input”. The terminal 5 inputs a clock signal CLK to the control circuit 806 through a buffer 809. The attribute of a terminal 7 is “output”, and the function allotted thereto is “data output”. Output data DO is output from the terminal 7 through a data output buffer 808. The attributes of terminals 3, 4 and 6 are “power supply”, and the functions allotted to the terminals 3, 4 and 6 are “connection to the ground potential”, “connection to the power supply potential” and “connection to the ground potential”, respectively. The attributes of terminals 8 and 9 are “high impedance”, and the terminals 8 and 9 are unused.
In the prior art semiconductor memory card 801, the functions according to the second operation mode are allotted to the terminals as described above. The semiconductor memory card 801 in the second operation mode performs data writing and reading with a host apparatus of the interface specification of the second operation mode. FIG. 8 does not show the connection structure of the interface circuit 804 in the first operation mode. In the first operation mode, the interface circuit 804 of the semiconductor memory card is structured based on the specification shown in FIG. 9. The semiconductor memory card in the first operation mode performs data writing and reading with a host apparatus of the interface specification of the first operation mode.
In the prior art semiconductor memory card, when data is transmitted, in the first operation mode, both “input” and “output” are allotted to one terminal (line), so that when data is transmitted in two directions at the same time, data collision occurs on one line. For this reason, high-speed data communication control of executing data transmission in two directions at the same time cannot be performed. The prior art semiconductor memory card uses the input clock input to the terminal 5 as it is as the clock for data output. Therefore, when the clock frequency is high, a timing shift between the data and the clock is caused on the receiving side (the host apparatus connected to the semiconductor memory card). Moreover, in the second operation mode, because of the presence of the unused terminals (lines), it cannot be said that terminals are efficiently used.
The present invention is made with an object of providing a semiconductor memory card enabling high-speed data communication control and being capable of eliminating a timing shift between the output data and the output clock on the receiving side (the host apparatus connected to the semiconductor memory card), a method of controlling the semiconductor memory card and an interface apparatus for semiconductor memory card.